Documentation pool for memory problem investigation

This is a set of documentation that relates directly to our SoC-board.

SoC: Atmel AT91SAM9G45

All related documents for SoC:
http://www.atmel.com/devices/SAM9G45.aspx?tab=documents

Full manual:
http://www.atmel.com/Images/doc6438.pdf

ARM 926 EJS core describes what does ARM core actually do to memory.
http://www.atmel.com/Images/ARM_926EJS_TRM.pdf

For example, p.144:

All burst reads and writes are performed by the ARM926EJ-S processor as word-wide transfers (HSIZE[2:0] = 010). Single reads and writes are performed as byte (HSIZE[2:0] = 000), halfword (HSIZE[2:0] = 001), or word wide transfers (HSIZE[2:0] = 010). 

Memory is Micron DDR2 MT47H32M16HR-25E IT (industrial version)
datasheet

Micron just random "how to perform well" manual:
Technical Note DDR2 (Point-to-Point) Features and Functionality

Atmel official recommendations for DDR2:
http://support.atmel.com/bin/customer.exe?=&action=viewKbEntry&id=900

Implementation of DDR2 on AT91SAM9G45 Devices (extract about features, configuration and initialization sequence).

Over-shoots occur when the current driven is too high. The SAM9G45 microprocessor embeds drive control on memory signals. Refer to the Product Datasheet for more details.

at91sam9g45 DDR controller half drive strength problem

I'm putting this material in blog so I could publish the same question in many places.

Choosing driver strength for DDR2 memory on at91sam9g45 SoC

Our ARM board uses at91sam9g45 SoC by Atmel. The board has 64 MB DDR2 memory, implemented on a single chip -- Micron MT47H32M16, connected to standalone DDR2 controller (DDRSDRC0, 0xFFFFE600).

As we have so called point-to-point configuration, it is supposed that working with memory is done with half driver strength of DDR controller.

UPDATE
The problem was solved. Actually, in this project we didn't really care if driver strength is correct, we just need the product to boot up and work, so if driver strength is wrong but there are no RAM errors. we're good.

So, the actual problem was improper power source for 1V CPU. We didn't look closely to reference power schematics, so we missed a capacitor that smoothes consumption pulses on 1V voltage.

Everything works ok now. The rest of the text is left for historical purposes.